1.
Micromachines (Basel)
; 14(10)2023 Sep 30.
Artigo
em Inglês
| MEDLINE
| ID: mdl-37893333
RESUMO
This paper proposes a unique memristor-based design scheme for a balanced ternary digital logic circuit. First, a design method of a single-variable logic function circuit is proposed. Then, by combining with a balanced ternary multiplexer, some common application-type combinational logic circuits are proposed, including a balanced ternary half adder, multiplier and numerical comparator. The above circuits are all simulated and verified in LTSpice, which demonstrate the feasibility of the proposed scheme.